This invention relates to a circuit for detecting whether a phase-locked loop circuit (hereinafter referred to as "a PLL circuit", when applicable) is in a synchronous state or an asynchronous state, and more particularly to such a detection circuit which is used to detect the time axis error of a reproduction signal in a recorded data reproducing device.
A recorded data reproducing device obtains a stable reproduction signal by using a circuit for detecting and correcting its time axis error. For instance, in a video disk player (VDP) for reproducing a color video signal, a so-called "tangential mirror" is driven by the phase error component of the horizontal synchronizing signal of the reproduction signal, to control the relative positions in the track-tangential direction of the record track and a pickup data detection point. The reproduction video signal obtained in this manner, however, includes a residual phase error. In order to correct this error, a circuit as shown in FIG. 1 is employed.
In FIG. 1, a burst gate circuit 1 extracts the 3.58 MHz color burst signal from a reproduction video signal, and a PLL circuit made up of a phase comparator 2, a loop filter 3 and a voltage-controlled oscillator (VCO) 4 detects the color burst phase. A signal which varies with the variation in phase of the reproduction color burst signal is obtained at the output of the phase comparator 2. As such, the detection output is used to cause a time axis controller 5 to correct the time axis of the reproduction video signal, to thereby compensate for the above-described residual phase error.
When the PLL circuit is in a synchronous state, it is necessary to change the frequency characteristic of the loop to a narrow band characteristic (for instance with a cut-off frequency of 30 Hz) so that it is not affected by high frequency noises or the like. Similarly, when the PLL is in an asynchronous state, it is necessary to change the frequency characteristic to a wide band characteristic (for instance having a cut-off frequency of 500 Hz) so that the lock-in operation is achieved more quickly. In order to meet this requirement, the synchronous state and the asynchronous state of the PLL circuit are detected, and the time constant of the loop filter 3 is changed, so that the loop bandwidth is varied. One example of a circuit for detecting the synchronous and asynchronous states of the PLL circuit is shown in FIG. 2. The output of the VCO 4 is phase-shifted as much as 90.degree. by a .pi./2 phase shifter 6, and is compared with a reproduction color burst signal in a phase comparator 7. The comparison output is converted into a DC signal by a low-pass filter (LPF) 8, which is applied to a level decision circuit 9. The level decision output is a synchronous/asynchronous state detection signal which controls the time constant of the loop filter 3.
In the synchronous state, the phase difference between the reproduction color burst signal and the VCO output signal is .pi./2. However, with the output of the phase shifter 6 being obtained by phase-shifting the VCO output signal by as much as .pi./2, the phase difference between the reproduction color burst signal and the output of the phase shifter 6 is .pi.. The output signal of the LPF 8, to which the output of the phase comparator 7 is applied, is maintained for instance at a high level. In the asynchronous state, the two inputs to the phase comparator 7 are random, and therefore the output of the LPF 8 is lower in level than in the synchronous state. Accordingly, whether or not the PLL circuit is in the synchronous state can be detected by comparing the output level of the LPF 8 with a predetermined reference level in the level decision unit 9.
However, in a VDP, the record disk is generally somewhat eccentric. Therefore, even in the synchronous state, the color burst signal will include phase error, due to the eccentricity, which has a component lower than 30 Hz (the component being 30 Hz in the case of a constant angular velocity (CAV) record disk system). Accordingly, it is difficult for the detecting circuit in FIG. 2 to accurately detect whether or not the PLL circuit is in the synchronous state.